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ABSTRACT

A DIGITAL PHASE SCALER FOR WEIGHTING THE DETECTED PHASE ERROR BETWEEN INPUT AND OUTPUT SIGNALS IN AN ALL DIGITAL PHASE LOCK LOOP SO THAT THE PROPER PHASE AND FREQUENCY CORRECTIONS ARE INITIATED. THE SCALER IS A DIGITAL LOGIC CIRCUIT WHICH ACCUMULATES THE PHASE ERRORS AND DECODES A PHASE CORRECTION PULSE AT A CONTROLLED VALUE OF THE ACCUMULATED PHASE ERRORS. THE SCALE MAY ALSO DECODE A FREQUENCY CORRECTION PULSE AT A CONTROLLED VALUE OF ACCUMULATED PHASE ERRORS. CONTROL POINTS ARE INCLUDED TO VARY THE WEIGHTING FUNCTION OF THE SCALER AND, HENCE, THE RESPONSE OF THE PHASE LOCK LOOP. THE SCALER IS IMPLEMENT IN TWO BASIC DESIGNS: A BINARY ADDER-TYPE SCALER, AND A BINARY COUNTER-TYPE SCALER.

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at therequest of the applicant or owner in accordance with the Notice of Dec.16, 1969, 869 O.G. 687. The abstracts of Defensive Publicationapplications are identified by distinctly numbered series and arearranged chronologically. The heading of each abstract indicates thenumber of pages of specification, including claims and sheets ofdrawings contained in the application as originally filed. The files ofthese applications are available to the public for inspection andreproduction may he purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to themerits of alleged invention. The Patent Ofiice makes no assertion as tothe novelty of the disclosed subject matter;

PUBLISHED NOVEMBER 23, 1971 T892,009 DIGITAL PHASE SCALER Robert F.Heidecker, Longmont, Colo., assignor to International Business MachinesCorporation, Armonk, NY.

Continuation of application Ser. No. 792,232, Jan. 15, 1969. Thisapplication Dec. 2, 1970, Ser. No. 94,558 Int. Cl. G06f 7/48 US. Cl.235-156 1 Sheet Drawing. 11 Pages Specification mg: I L" MDE BY m summerAEtUWLAlOR uumm BY 1 A digital phase sealer for weighting the detectedphase error between input and output signals in an all digital phaselock loop so that the proper phase and frequency corrections areinitiated. The scaler is a digital logic circuit which accumulates thephase errors and decodes a phase correction pulse at a controlled valueof the ac cumulated phase errors. The sealer may also decode a frequencycorrection pulse at a controlled value of accumulated phase errors.Control points are included to vary the weighting function of the sealerand, hence, the response of the phase lock loop. The sealer isimplemented in two basic designs: a binary adder-type scaler, and abinary counter-type sealer.

Nmr. 23, E971 R, F m c TZMOQ DIGITAL PHASE SCALER if Filed Dec. 2, 19701o 12 9 ADD l SUBTRACT ACCUMULATOR F mvmF 1 BY CORRECTISNJ 1s 20 1sMULTIPLY BY m DETECTED PHASE )ERROR INPUT 3a SUBTRACT 1 39 w g) 36\ K2 IPW l H5 a --4 I a; 1 i2 M-4 ooRREcnoR PULSE 6 OUTPUT THRESHOLD DECODE(K1) DEOODER PHASE CORRECTION m A 38\ A r: l MM F R I FF F FF FF ERROR 1F2 4 8 I 1 46 I Q E i 0 L I a I A I R R R R LM M in J A R j 48) AFREQUENCY CORRECTION INVENTOR ROBERTE HEIDECKER B I, d

